>> Verify the solution

To verify whether the patch has been applied successfully and is working as expected, we can examine the register value at DisplayPort address 0x100 in addition to no sign of a kernel panic. According to the DisplayPort specification, 0x100 is the address of the LINK_BW_SET register and therefore the graphics driver (i.e. the source) is required to write the final link rate value to it. Fortunately, Apple provides a command line tool named AGDCDiagnose to dump values at some ranges of DisplayPort addresses. It also prints other information related to the graphics devices and the drivers, but right now we only focus on the DPCD data.

You may find AGDCDiagnose in /System/Library/Extensions/AppleGraphicsControl.kext/Contents/MacOS/ and use AGDCDiagnose -a to dump all data.

//
// Sample report generated by AGDCDiagnose (Version: 3.25.6)
//
// Notes: 
// (1) Some "irrelevant" lines are omitted in the below report.
// (2) Test environment: Intel Iris Pro Graphics 580 with a 1080p display connected.
//                       macOS Mojave 10.14.1 (18B75)
//                       Skylake Intel(R) Core(TM) i7-6770HQ CPU
// 
## Register Dump Port 4 - Start ## 
- 000000: 0x11 0x0a 0x84 0x01 0x01 0x00 0x01 0x00 0x02 0x02 0x06 0x00 0x00 0x00 0x00 0x00
Reg: 000000: 11 : DPCD_REV: 1.1
Reg: 000001: 0a : MAX_LINK_RATE: HBR
Reg: 000002: 84 : MAX_LANE_COUNT: 4, TPS3_SUPPORTED: 0, ENHANCED_FRAME_CAP: 1
Reg: 000003: 01 : MAX_DOWNSPREAD: 0.5% down, NO_AUX_HANDSHAKE_LINK_TRAINING: 0
Reg: 000004: 01 : NORP: 1
Reg: 000005: 00 : DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT: 0, 
                                          DWN_STRM_PORT_TYPE: [0] DisplayPort, 
                                          FORMAT_CONVERSION: 0, 
                                          DETAILED_CAP_INFO_AVAILABLE: 0
Reg: 000006: 01 : MAIN_LINK_CHANNEL_CODING: ANSI 8B/10B
Reg: 000007: 00 : DOWN_STREAM_PORT_COUNT: DWN_STRM_PORT_COUNT: 0, MSA_TIMING_PAR_IGNORED: 0, OUI: 0
Reg: 000008: 02 : RECEIVE_PORT0_CAP_0: LOCAL_EDID_PRESENT: 1, ASSOCIATED_TO_PRECEDING_PORT: 0
Reg: 000009: 02 : RECEIVE_PORT0_CAP_1: BUFFER_SIZE: 96
Reg: 00000a: 06 : RECEIVE_PORT1_CAP_0:
Reg: 00000b: 00 : RECEIVE_PORT1_CAP_1:
Reg: 00000c: 00 : I2C Speed: 
Reg: 00000d: 00 : eDP_CONFIGURATION_CAP: ALTERNATE_SCRAMBLER_RESET_CAPABLE: 0, FRAMING_CHANGE_CAPABLE: 0
Reg: 00000e: 00 : TRAINING_AUX_RD_INTERVAL: 100 us, EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT: NO
Reg: 00000f: 00 : ADAPTER_CAP: FORCE_LOAD_SENSE_CAP: 0, ALTERNATE_I2C_PATTERN_CAP: 0

- 000100: 0x0a 0x84
Reg: 000100: 0a : LINK_BW_SET: HBR
Reg: 000101: 84 : LANE_COUNT_SET: LANE_COUNT_SET 4, ENHANCED_FRAME_EN: 1

Let's first learn how to interpret the report by looking at a sample. The above report is obtained from an Intel Skull Canyon NUC equipped with Intel Iris Pro Graphics 580 and a 1080p display connected via a DisplayPort cable. This is the case where the connected display reports a valid link rate value and everything works as expected.

16 bytes are read from the DisplayPort address at 0x0, which represents the first 16 capabilities of the connected display and corresponds to the dpcd_caps buffer in GetDPCDInfo() function. On the other hand, 2 bytes are read from 0x100, indicating how the graphics driver configures the link between the GPU and the display. We only focus on aforementioned registers, and you can find detailed descriptions for the rest registers in the specification if you are interested in them.

You can see that the MAX_LINK_RATE value (at address 0x1) is 0x0A, indicating that the display cannot support a link that has a rate greater than 0x0A. As a result, the graphics driver set the final link rate, namely the LINK_BW_SET register at address 0x100 to 0x0A.

In comparison, another sample report is generated when a 4K display is connected to the same NUC. Now a higher value of MAX_LINK_RATE is reported in order to light up the 4K display.

// TODO: ADD THE SAMPLE REPORT GENERATED ON A 4K DISPLAY

Now let's take a look at the report generated on a problematic laptop. This is the case where the internal display does not report a valid link rate value and therefore causes GetDPCDInfo() failing to return 0.

//
// Sample report generated by AGDCDiagnose (Version: 3.28.4)
//
// Notes: 
// (1) Some "irrelevant" lines are omitted in the below report.
// (2) Test environment: Intel UHD Graphics 630 with the built-in 4K display
//                       macOS Mojave 10.14.2 Beta 2 (18C38b)
//                       Coffee Lake Intel(R) Core(TM) i7-8750H CPU
// 
## Register Dump Port 1 - Start ## 
- 000000: 0x14 0x00 0xc4 0xc1 0x00 0x00 0x01 0xc0 0x02 0x00 0x00 0x00 0x00 0x0b 0x00 0x00
Reg: 000000: 14 : DPCD_REV: 1.4
Reg: 000001: 00 : MAX_LINK_RATE: ???
Reg: 000002: c4 : MAX_LANE_COUNT: 4, TPS3_SUPPORTED: 1, ENHANCED_FRAME_CAP: 1
Reg: 000003: c1 : MAX_DOWNSPREAD: 0.5% down, NO_AUX_HANDSHAKE_LINK_TRAINING: 1
Reg: 000004: 00 : NORP: 0
Reg: 000005: 00 : DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT: 0, 
                                          DWN_STRM_PORT_TYPE: [0] DisplayPort, 
                                          FORMAT_CONVERSION: 0, 
                                          DETAILED_CAP_INFO_AVAILABLE: 0
Reg: 000006: 01 : MAIN_LINK_CHANNEL_CODING: ANSI 8B/10B
Reg: 000007: c0 : DOWN_STREAM_PORT_COUNT: DWN_STRM_PORT_COUNT: 0, MSA_TIMING_PAR_IGNORED: 1, OUI: 1
Reg: 000008: 02 : RECEIVE_PORT0_CAP_0: LOCAL_EDID_PRESENT: 1, ASSOCIATED_TO_PRECEDING_PORT: 0
Reg: 000009: 00 : RECEIVE_PORT0_CAP_1: BUFFER_SIZE: 32
Reg: 00000a: 00 : RECEIVE_PORT1_CAP_0:
Reg: 00000b: 00 : RECEIVE_PORT1_CAP_1:
Reg: 00000c: 00 : I2C Speed: 
Reg: 00000d: 0b : eDP_CONFIGURATION_CAP: ALTERNATE_SCRAMBLER_RESET_CAPABLE: 1, FRAMING_CHANGE_CAPABLE: 1
Reg: 00000e: 00 : TRAINING_AUX_RD_INTERVAL: 100 us, EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT: NO
Reg: 00000f: 00 : ADAPTER_CAP: FORCE_LOAD_SENSE_CAP: 0, ALTERNATE_I2C_PATTERN_CAP: 0

- 000100: 0x14 0x84
Reg: 000100: 14 : LINK_BW_SET: HBR2
Reg: 000101: 84 : LANE_COUNT_SET: LANE_COUNT_SET 4, ENHANCED_FRAME_EN: 1

The MAX_LINK_RATE register reports an invalid value of 0x00, but the graphics driver has set 0x14 to the LINK_BW_SET register, indicating that the patch has been applied successfully and is working as expected.

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